1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
In recent years, developments in large scale integrated circuits (LSI) having analog-circuits (analog devices) and digital circuits (digital devices) integrated in one chip is progressed. Among these technical trends, miniaturizations of digital devices are progressed year by year, in which a reduced gate length in a metal oxide semiconductor (MOS) transistor of on the order of about 0.1 μm was achieved, and in such situation, copper (Cu), which is a low resistivity material, has widely been employed for an interconnect material, for the purpose of providing a reduced interconnect resistance, and a damascene process has been employed for forming the interconnects.
Meanwhile, capacitor elements are critical components for analog circuits. While a capacitor element has been conventionally configured to have a polysilicon layer or an impurity diffusion layer employed as an electrode, a type of a capacitor element so called metal-insulator-metal (MIM) capacitor newly attracts attention in recent years. The MIM capacitor is a capacitor element, which is configured by providing an insulating film sandwiched between electrodes that are composed of a metal, and draws much attention since the MIM capacitor is capable of providing an improved frequency characteristics. When Cu is employed for an interconnect material, Cu is also often employed for an electrode of a MIM capacitor.
Nonetheless, when an electrode of a MIM capacitor is formed via a damascene process employing Cu for a material of the process, a problem of a dishing (phenomenon of causing positional variation in polishing-ability in a planarizing operation of a Cu interconnect via a chemical mechanical polishing (CMP) process, and more specifically a center of an interconnect is more considerably polished as compared with both ends of the interconnect, leading to a locally thinner interconnect film in the center) is caused, so that a process for forming the MIM capacitor without causing an issue of the dishing is expected. In particular, since degree of integration in a transistor is increasingly improved as levels of the miniaturization is increased, a critical issue is how the capacitor elements in an analog circuit would be formed to have higher capacity without disturbing higher integration level of devices. In addition, since characteristics of the integrated analog circuits are increasingly improved, a formation of capacitor elements with less variation of capacities is a critical problem for the purpose of providing improved characteristics of analog circuits.
A conventional structure for preventing such issue of dishing caused in the process for forming the electrode in the MIM capacitor is described in Japanese Patent Laid-Open No. 2001-237,375. FIG. 18 illustrates a plan view of a MIM capacitor disclosed in Japanese Patent Laid-Open No. 2001-237,375. FIG. 19 is a cross-sectional view along line A-A′ of FIG. 18. In the semiconductor substrate 211, a lattice-shaped trench is formed, and the interior of this trench is filled with a metallic film 212 composed of a metallic material having lower resistance (for example, Cu). The metallic film 212 filling the interior of the trench in the semiconductor substrate 211 serves as a first electrode of the MIM capacitor. While the layout of the first electrode in the MIM capacitor is designed to be lattice-shaped, such layout is for solving the issue of the dishing in the damascene process.
A silicon nitride (SiN) film 213 is formed on the semiconductor substrate 211 except a region to be provided with a capacitor of the MIM capacitor. The region to be provided with a capacitor of the MIM capacitor forms a groove surrounded by the walls of the silicon nitride film 213. Then, a tungsten nitride (WN) film 214 is formed in the region to be provided with a capacitor of the MIM capacitor. The tungsten nitride film 214 functions as a diffusion barrier film for the metallic film 212, and also functions as increasing the capacitor area by being disposed above the lattice-shaped first electrode.
A capacitor insulating film (for example, tantalum oxide (Ta2O5) film) 215 is formed on the tungsten nitride film 214. A tungsten nitride (WN) film 216 is formed on the capacitor insulating film 215. The tungsten nitride film 216 functions as a diffusion barrier film for a metallic material (for example, Cu) serving as a second electrode of the MIM capacitor as described later and also functions as increasing the capacitor area by being disposed under the lattice-shaped second electrode.
A silicon nitride (SiN) film 217 is formed on the tungsten nitride film 216. The silicon nitride film 217 functions as an etch stop film in the etch process (i.e., in the process for forming trench), together with the silicon nitride film 213.
A silicon oxide (SiO2) film 218 is formed on the silicon nitride films 213 and 217, and a silicon nitride film 219 is formed on the silicon oxide film 218. The silicon nitride film 219 functions as an etch stop film in the process for forming the trench in the ducal damascene process. A silicon oxide (SiO2) film 220 is formed on the silicon nitride film 219, and a silicon nitride film 221 is formed on the silicon oxide film 220. The silicon nitride film 221 functions as an etch stop film in the CMP process.
A lattice-shaped trench, or a trench for an interconnect or a pad, for example, is formed within the silicon oxide film 220 (portion thereof above the silicon nitride film 219). In addition, trenches (via holes) that reach to the metallic film 212 or the tungsten nitride film 216 are formed in the silicon oxide film 218 and the silicon nitride film 213. The interior of these trenches are filled with metallic films 222A and 222B, which are composed of a metallic material having lower resistance and larger diffusion constant (for example, Cu). The metallic film 222A filling the interior of the trench serves as a second electrode of the MIM capacitor.
However, an issue of increasing a manufacturing cost described as follows may be caused in such technique. More specifically, while the first electrode of the MIM capacitor composed of the metallic film 212 is formed to be lattice-shaped, the tungsten nitride film 214 is formed to be flat-shaped in the region to be provided with capacitors. In addition, while the tungsten nitride film 216 is formed to be flat-shaped on the capacitor insulating film 215, the second electrode of the MIM capacitor composed of the metallic film 222A is formed to be lattice-shaped.
Since the tungsten nitride films 214 are 216 are formed under and above the capacitor insulating film 215, respectively, the tungsten nitride films 214 and 216 substantially constitutes electrodes of the MIM capacitor. As described above, the operation for forming the metallic films 212 and 222A to be lattice-shaped and the operation for forming the tungsten nitride films 214 and 216 to be flat-shaped are required to form the electrodes of the MIM capacitor, leading to a problem of an increased number of the process operations and thus an increased manufacturing cost.